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ZHILIUDIANJI
- EDA直流电机项目设计,能实现加速 减速 方向控制。-EDA DC project design, to achieve directional control of accelerating and decelerating.
viterbi213
- 编码方式为213的Viterbi卷积码编码器和译码器的FPGA的实现,包含整个QuartusII的工程文件,解码方式为寄存器交换法-Encoding for the 213 convolutional code encoder and Viterbi decoder FPGA realization of the project file that contains the entire QuartusII, decoding method for the register exchange
DE2_70_AUDIO
- 是用VERILOG HDL和NIOS II C/C++ 编的DE2-70板子的音频编解码芯片的使用工程-Is VERILOG HDL and NIOS II C/C++ code of the DE2-70 board in the audio codec chip, the use of project
crc
- crc project by vhdl -crc project by vhdl ..............
cpu
- 设计以及基本的CPU,至少包括四个基本单元,控制单元,内部寄存器,ALU和指令集-The purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to generate a very simple program to verify its perf
UART_prj_ViHDL
- vhdl project at sbu uni in iran uart
64R4SDFpoint_FFT
- 该工程实现了一个64点FFT,verilog编写,采用R4SDF结构,通过Modelsim功能仿真,压缩包里有rtl代码,dc脚本,输出报告。-The project implements a 64-point FFT, verilog compiled by R4SDF structure, through the Modelsim functional simulation, compression bag with rtl code, dc scr ipt, the output repo
64pointFFTR2MDC
- 该工程实现了一个64点DIF FFT,verilog编写,采用R2MDC结构,通过Modelsim功能仿真,压缩包里有rtl代码,dc脚本,输出报告。-The project implements a 64-point DIF FFT, verilog compiled by R2MDC structure, through the Modelsim functional simulation, compression bag with rtl code, dc scr ipt, the out
vcsVHDL
- 用VCS进行VHDL开发的一些文档,很有用的哦-some document for exploere VHDL project with VCS
project
- 介绍了利用VHDL硬件描述语言设计的简易数字钟的思路和技巧。在QuatusⅡ开发环境中编译和仿真了所设计的程序,并在可编程逻辑器件上下载验证。仿真和验证结果表明,该设计方法切实可行,具有一定的借鉴性。-digital clock
IFFT
- 这是关于傅里叶反变换的一个完整的ISE的工程..使用verilog语言-This is on the Fourier transform of a complete anti-ISE project using the verilog language ..
DMX512_2_23
- 本系统设计利用FPGA设计了一个接在电脑串口上的一个DMX512协议的转接卡,它可以让你的电脑变成一台超强的电脑灯控制台或者调光台、LED控制器等。通过电脑软件,可以控制电脑灯或者其他DMX512协议的设备,比如LED灯、激光灯、PAR灯、DJ设备等等。 本系统还有体积小巧携带方便等特点,足够一般的娱乐场所、多功能厅、会议厅等场所使用,同时采用电脑进行灯光的控制,也可以提升工程的技术含量,显得更高科技。通过简单更改DMX模块的UART部分,还可以将串口转换usb接口,不过由于手头上的FPGA
project
- vhdl souce code for simple basic components
project
- dsp lab programs using vhdl
hdbn
- HDBN VHDL Project includes hdb3 & hdbn
vhdl
- 慢码的vhdl,编码,解码,现在在做一个红外线的project.RC5 生成一个信号个给检测器,检测器会产生一组14 bits的数据流(是一组 曼彻斯特编码)。想用VHDL做一个解码器。-Slow code vhdl
sipo8
- 串入并出源代码,可进行8位数据的串/并转换。其中包括QUARTUS2的完整工程,有正确的仿真波形供参考。-In series and the source code, can be 8-bit data series/parallel conversion. Including QUARTUS2 complete project,and the correct simulation waveform for reference.
piso8
- 并/串转换的VHDL源代码,其中包括完整的QUARTUS2工程,还有正确的仿真波形。串行,并行数据 -Serial/parallel conversion ,VHDL source code, including complete QUARTUS2 project, and the correct simulation waveform file.
fpu100_latest.tar
- This a 32-bit floating point unit (FPU), which I developed in a project within the Vienna University of Technology. It can do arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard-This is a 32-bit floating
VHDL-quick-start
- descr iption of VHDL Quick introduction to VHDL – basic language concepts – basic design methodology • Use The Student’s Guide to VHDL or The Designer’s Guide to VHDL – self-learning for more depth – reference for project work-desc